In general, the design of digital integrated circuits includes two main design phases such as, for example, an RTL (register transfer level) design phase and a physical design phase. An RTL design phase is performed by converting a user specification of integrated circuit function into an RTL description, which specifies how each portion of the integrated circuit operates on each clock cycle. In the physical design phase, an integrated circuit design is generated using a corresponding RTL file and a library of standard component cells such as basic logic gates (AND gate, OR gates, NAND gates, NOR gates, etc.) and macro cells such as adders, multiplexers, flip-flops, memory, etc. More specifically, a physical design phase includes various phases such as logic synthesis, placement, clock-tree synthesis, and routing.
By design, transmission gate logic cells have fewer transistors than conventional CMOS (complementary metal oxide semiconductor) cells and, therefore, transmission gate logic cells are smaller, lower power and generally faster. However, transmission gate logic cells have certain properties such as state-dependent timing input loading and multi-port-dependent timing arcs, which preclude the use of transmission gate logic cells in standard, fast-turn application specific integrated circuit design flows. Indeed, the use of transmission gate logic cells in circuit design is limited to large-scale, full transistor-level custom design circuits and flows.